[Starpu-devel] handles without sequential consistency, RW access mode and multiple memory nodes

[Jean-Marie Couteyen <jean-marie.couteyen@inria.fr>]

Hello,

I discussed with Abdou about disabling sequential consistency for 
handles and expressing dependencies another way (actually by having some 
'symbolic void handles' and sequential consistency enabled for them, in 
order to reduce the cost of implicit dependencies - I have a lot of 
handles that are accessed in the same way)

Conditions : Handle H accessed in RW by several task (T1, T2), no 
sequential consistency for H, multiple memory nodes(M1, M2). T1 is 
executed on M1 and T2 on M2 (let's say we have only GPU impl for T2 and 
only CPU impl for T1 ). No dependency between T1 and T2 and they can be 
executed in any order (T1 then T2 is valid, T2 then T1 is valid too).

What if a given handle (H) is accessed in RW by several tasks that have 
their dependencies fulfilled ?

*First, I though that there was a safeguard that did not allow other 
tasks having H around its data to be ready when a task having H in W 
mode was ready or executing. So T1 or T2 can be scheduled or executed 
but not the two of them at the same time. Let's say it's T1.

*Then, I though that the MSI protocol was in charge to invalidate all 
the others copies (only M2 in our case) because of the W access, so that 
when T2 is executed, a memory transfer take place and the data 
associated with H is up-to-date in M2 before T2 execution.

Is this right ?

Regards,
Jean-Marie